Modern processors often include instructions to provide operations that are computationally intensive, but offer a high level of data parallelism that can be exploited through an efficient implementation using various data storage devices, such as for example, single instruction multiple data (SIMD) vector registers.
For some algorithms such a high level of data parallelism cannot be exploited, and so the vector resources are under utilized.
On the other hand, fault tolerance and fault detection features are not typically applied to data-transformation units such as arithmetic-logic units (ALUs) in high-production processors because the implementation costs exceed the benefit. However, reducing the dimensions and increasing the number of transistors in a package, while making devices faster and more efficient, increases the probability of faults due to alpha particles and other causal factors.
Additionally, there are some extreme environments in which fault tolerance is a highly desirable feature of computer systems. For example, a configurable fault tolerant processor (CFTP) was developed by the Space Systems Academic Group at the Naval Postgraduate School using field programmable gate arrays (FPGAs). It was then deployed as an experimental payload on board the United States Naval Academy's (USNA) MidSTAR-1 satellite. A second CFTP system, CFTP-2, was deployed as an entirely ground-based system and was tested in a proton beam using the University of California at Davis' cyclotron.
Such FPGA implementations may limit performance advantages otherwise available for example, from very-large-scale integration (VLSI) and their implementations may additionally be larger and/or heavier, and may require higher supply voltages.
To date, potential solutions to such performance and efficiency limiting issues have not been adequately explored.